I. Technical Field
Embodiments described herein relate to spread spectrum ADC (analog-to-digital converter) noise reduction.
II. Background Art
Various existing products and services use analog-to-digital (A/D) converters (ADCs) for analog-to-digital conversion operations. However, transistor noise (e.g., “l/f” or low-frequency noise, e.g., 100 kHz-1 MHz or 1 MHz-10 MHz by system) becomes more severe with technology downward scaling and poses a steep trade-off with other design objectives such as speed and power. ADC l/f noise often does not significantly affect the integrated noise and the overall signal-to-noise ratio (SNR), however low-frequency noise degrades the SNR within the low frequency range which is problematic in some systems. Additionally, typical interleaved ADCs up-convert low-frequency noise to the multiples Fs/N (where Fs is the combined frequency of the interleaved lanes and N is the interleaving factor) which degrades the narrow-band SNR around the multiples of Fs/N. This may cause problems such as channel SNR degradation in some systems.
Various techniques have been used to compensate for ADC low-frequency noise. For example, transistor sizes may be scaled up to reduce low-frequency noise, though this leads to larger transistors, which may degrade other aspects of circuit performances such as speed and power. Correlated double sampling (CDS) techniques sample noise before sampling the signal plus noise in order to remove the noise, though they reduce the sample rate of the signal by half and increase the high-frequency noise present in the system. Auto-zeroing senses the low-frequency noise in a calibration phase and subtracts the noise during the normal operation, but the extra calibration phase reduces the conversion speed and the subtraction may introduce additional noise. Chopper stabilization (or chopping) modulates the signal with a fixed frequency square wave and shifts the low-frequency noise to a higher frequency, though it does not work for Nyquist ADCs. Interleaved ADC randomization with redundant lanes can be used, but leads to larger area, higher power, and clocking complexity.